The present invention relates to a clock recovery circuit being of high speed and low jitter in which a clock signal can be recovered by a clock signal of 1/xcfx80 frequency of the data rate xe2x80x9cnxe2x80x9d bps (bit per second) of inputted serial random data and a phase detecting method which can realize this clock recovery circuit.
FIG. 1 is a block diagram showing a conventional clock recovery circuit. As shown in FIG. 1, the conventional clock recovery circuit consists of a phase detector (PD) 101 which receives inputted serial random data having the data rate of xe2x80x9cfxe2x80x9d bps and compares the phase of a clock signal oscillating about xe2x80x9cfxe2x80x9d Hz generated by a voltage controlled oscillator (VCO) 104 with the phase of the received inputted serial random data, a charge pump (CP) 102 which receives up pulses and down pulses showing the result of the phase comparison at the PD 101 and supplies charge/discharge current in response to the up and down pulses to a loop filter (LPF) 103, the LPF 103 which removes unnecessary noise included in the output from the PD 101, and the VCO 104 which makes the oscillating frequency change in response to the charge/discharge current that is outputted from the CP 102 and is removed the noise at the LPF 103.
Generally, a Hogge type phase detector is used for comparing the phase of the inputted serial random data having the data rate of xe2x80x9cfxe2x80x9d bps with the phase of the clock signal of xe2x80x9cfxe2x80x9d Hz. FIG. 2 is a block diagram showing the Hogge type phase detector used for the conventional clock recovery circuit and a timing chart of output signals from the functions shown in FIG. 1. Referring to FIG. 2, structure and operation of the Hogge type phase detector are explained. The timing chart in FIG. 2 shows signal output timing of each function at the time when the clock signal lagged and led for the inputted serial random data and is synchronized with the inputted serial random data.
As shown in FIG. 2, the Hogge type phase detector consists of a delayed flip flop (F/F) 105 to which the serial random data and a clock signal (hereinafter referred to as CLK) A from a VCO (not shown) are inputted, an inverter 110 which inverts the CLK A, a delayed flip flop (F/F) 106 to which the output from the F/F 105 and a CLK B inverted the CLK A at the inverter 110 are inputted, an exclusive-or (EX-OR) circuit 107 to which the serial random data and the output from the F/F 105 are inputted, an EX-OR circuit 108 to which the outputs from the F/Fs 105 and 106 are inputted, and an inverter 109 which inverts the output from the EX-OR circuit 107.
At the Hogge type phase detector mentioned above, the EX-OR circuit 107 applies EX-OR for the waveform of the inputted serial random data and the waveform of the output from the F/F 105 which the CLK A is applied to the serial random data received at the F/F 105. The output from the EX-OR circuit 107 is inverted at the inverter 109 and outputted, this output is named as UP pulses (the waveform of the EX-OR 107 in FIG. 2).
And the EX-OR circuit 108 applies EX-OR for the waveform of the output from the F/F 105 and the waveform of the output from the F/F 106 which the CLK B is applied to the output from the F/F 105 at the F/F 106. The output from the EX-OR circuit 108 is named as DOWN pulses (the waveform of the EX-OR 108 in FIG. 2).
Referring to the waveforms of pulses shown in FIG. 2, the mentioned above UP and DOWN pulses are explained in cases that the phase of the clock signal lagged and led for the inputted serial random data, and is synchronized with the inputted serial random data. In this, the synchronized state is that the rising edge of the CLK A is at the center of the data.
As shown in FIG. 2, the width of the DOWN pulses is always constant at the time when the phase of the clock signal lagged or led for the inputted serial random data and are synchronized with the inputted serial random data. And the width of the DOWN pulses is xc2xd of the inputted serial random data.
On the other hand, the width of the UP pulses varies. That is, in case that the phase of the clock signal lagged for the inputted serial random data, the width is wide, in case that the phase of the clock signal is synchronized with inputted serial random data, the width is the same as the DOWN pulse, and in case that the phase of the clock signal led for the inputted serial random data, the width is narrow. In FIG. 2, the UP pulse is shown as a convex shape to the downward direction, and xcex8e shows the phase difference between the clock signal and the inputted serial random data.
The net difference between the widths of the UP and DOWN pluses is used for a charging/discharging current to the LPF 103 through the CP 102. That is, when the phase of the clock signal lagged, the net width of the UP pulse becomes large, when the phase of the clock signal led, the net width of the DOWN pulse becomes large. And when the phase of the clock signal is synchronized with the phase of the inputted serial random data, the net difference between the widths of the UP and DOWN pulses becomes xe2x80x9c0xe2x80x9d.
However, at the Hogge type phase detector mentioned above, as shown in FIG. 2, even when the phase of the clock signal is synchronized with the inputted serial random data, a large current flows through the CP 102 in response to the UP and DOWN pulses, therefore, there is a problem that the jitter characteristic at the synchronized state is deteriorated.
It is therefore an object of the present invention to provide a clock recovery circuit and a phase detecting method used for this circuit, in which a current flowing through a charge pump is made to zero at the time when the clock recovery circuit is synchronized, and the jitter characteristic is improved at the time when the clock recovery circuit is synchronized. And further another object of the present invention is to provide a clock recovery circuit and a phase detecting method used for this circuit which can perform high speed clock recovery not controlled by any oscillating frequency of a voltage controlled oscillator.
According to a first aspect of the present invention, for achieving the objects mentioned above, there is provided a clock recovery circuit. The clock recovery circuit provides multi phase clock signal generating means which generates a reference clock signal whose frequency is controlled to be about f/2 Hz for inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bit per second (bps), and also generates a plurality of clock pulses whose phases are different from the reference clock signal, edge detecting means for detecting rising edges and falling edges of the inputted serial random data, detected edge selecting means which selects whether the detected edges of the inputted serial random data are compared their phases with rising edges or falling edges of the reference clock signal, and outputs first edge pulses synchronized with edges which are judged to be compared their phases with the rising edges of the reference clock signal and second edge pulses synchronized with edges which are judged to be compared their phases with the falling edges of the reference clock signal, first edge position correction for comparing edges means which corrects so that the frequency of a first clock pulse becomes equal to the frequency of the first edge pulses by selecting only edges of the first clock pulses which perform phase comparison with the first edge pulses in the edges of the first clock pulses which are used at the phase comparison with the rising edges of the reference clock signal, and also makes edges of the first edge pulses lag by phase difference between the reference clock signal and the first clock pulse, second edge position correction for comparing edges means which corrects so that the frequency of a second clock pulse becomes equal to the frequency of the second edge pulses by selecting only edges of the second clock pulses which perform phase comparison with the second edge pulses in the edges of the second clock pulses which are used at the phase comparison with the falling edges of the reference clock signal, and also makes edges of the second edge pulses lag by phase difference between the reference clock signal and the second clock pulse, first phase frequency detecting means which compares phases between the first clock pulse whose frequency is equal to the frequency of the first edge pulses, outputted from the first edge position correction for comparing edges means, and the first edge pulses whose phases are made to lag by the phase difference, and outputs pulses of the pulse widths in proportion to the phase difference between the both compared pulses, and second phase frequency detecting means which compares phases between the second clock pulse whose frequency is equal to the frequency of the second edge pulses, outputted from the second edge position correction for comparing edges means, and the first edge pulses whose phases are made to lag by the phase difference, and outputs pulses of the pulse widths in proportion to the phase difference between the both compared pulses.
According to a second aspect of the present invention, in the first aspect, the plurality of clock pulses whose phases are different from the reference clock signal whose cycle is 2xcfx80 is composed of a first clock pulse whose phase lags by xcfx80/2 for the reference clock signal and a second clock pulse whose phase leads by xcfx80/2 for the reference clock signal, and the edge detecting means provides a delay circuit which makes the phase of the inputted serial random data lag, and an exclusive-or (EX-OR) circuit to which the inputted serial random data and pulses that the inputted serial random data are made to lag at the delay circuit are inputted, and the detected edge selecting means provides a first AND circuit to which edge pulses being synchronized with rising edges and falling edges of the inputted serial random data outputted from the EX-OR circuit and the first clock pulse are inputted, and a second AND circuit to which edge pulses being synchronized with rising edges and falling edges of the inputted serial random data outputted from the EX-OR circuit and the second clock pulse are inputted, and the first edge position correction for comparing edges means provides a first set-reset flip flop (SR-F/F) whose set terminal pulses outputted from the first AND circuit are inputted to and whose reset terminal the first clock pulse is inputted to, and a first delay circuit which makes the pulses outputted from the first SR-F/F lag by xcfx80/2 phase, and the second edge position correction for comparing edges means provides a second SR-F/F whose set terminal pulses outputted from the second AND circuit are inputted to and whose reset terminal the second clock pulse is inputted to, and a second delay circuit which makes the pulses outputted from the second SR-F/F lag by xcfx80/2 phase, and the first phase frequency detecting (PFD) means compares phases between pulses outputted from the first delay circuit and an inverted output pulse from the first SR-F/F, and the second PFD means compares phases between pulses outputted from the second delay circuit and an inverted output pulse from the second SR-F/F.
According to a third aspect of the present invention, in the first aspect, the plurality of clock pulses whose phases are different from the reference clock signal whose cycle is 2xcfx80 is composed of a first clock pulse whose phase lags by xcfx80/2 for the reference clock signal and a second clock pulse whose phase leads by xcfx80/2 for the reference clock signal, and the edge detecting means and the detected edge selecting means provides a first AND circuit to which the inputted serial random data, and pulses made to lag and inverted the inputted serial random data, and the second clock pulse are inputted, and a second AND circuit to which the inputted serial random data, and pulses made to lag and inverted the inputted serial random data, and the first clock pulse are inputted, and a third AND circuit to which inverted the inputted serial random data, and pulses made to lag the inputted serial random data, and the second clock pulse are inputted, and a fourth AND circuit to which inverted the inputted serial random data, and pulses made to lag the inputted serial random data, and the first clock pulse are inputted, and a first OR circuit to which outputs from the first and third AND circuits are inputted, and a second OR circuit to which outputs from the second and fourth AND circuits are inputted, and the first edge position correction for comparing edges means provides a first SR-F/F whose set terminal pulses outputted from the second OR circuit are inputted to and whose reset terminal the first clock pulse is inputted to, and a first delay circuit which makes the pulses outputted from the first SR-F/F lag by xcfx80/2 phase, and the second edge position correction for comparing edges means provides a second SR-F/F whose set terminal pulses outputted from the first OR circuit are inputted to and whose reset terminal the second clock pulse is inputted to, and a second delay circuit which makes the pulses outputted from the second SR-F/F lag by xcfx80/2 phase, and the first PFD means compares phases between pulses outputted from the first delay circuit and an inverted output pulse from the first SR-F/F, and the second PFD means compares phases between pulses outputted from the second delay circuit and an inverted output pulse from the second SR-F/F.
According to a fourth aspect of the present invention, there is provided a clock recovery circuit. The clock recovery circuit provides multi phase clock signal generating means which generates a plurality of reference clock signals whose phases are serially different respectively and whose frequency is controlled to be about f/n Hz (n is an integer) for inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bit per second (bps), and also generates a plurality of clock pulses whose phases are different from the plurality of reference clock signals by a designated value respectively, edge detecting means which detects rising edges and falling edges of the inputted serial random data and generates edge pulses synchronized with the rising and falling edges, detected edge selecting means which selects that the detected edges of the inputted serial random data at the edge detecting means are compared their phases with any of the reference clock signals generated at the multi phase clock generating means, and outputs edge pulses synchronized with selected edges of the inputted serial random data in each of the reference clock signals, edge position correction for comparing edges means which corrects so that the frequency of the clock pulses becomes equal to the frequency of edge pulses by selecting only edges using for phase comparison with the edge pulses in the edges of the clock pulses set each of the reference clock signals which are used at the phase comparison with edge pulses generated each of the reference clock signals, and also makes edges of the edge pulses lag by phase difference between the reference clock signals and the clock pulses set each of the reference clock signals, and phase frequency detecting means which compares phases between the clock pulses whose frequency is equal to the frequency of the edge pulses, outputted from the edge position correction for comparing edges means, and the edge pulses whose phases are made to lag by the phase difference, and outputs pulses of the pulse widths in proportion to the phase difference between the both compared pulses.
According to a fifth aspect of the present invention, in the fourth aspect, the reference clock signals whose cycle is 2xcfx80 are composed of eight clock signals shifted by xcfx80/4 phase respectively, and the clock pulses are composed of eight clock pulses lagged by xcfx80/8 phase for each of the reference clock signals, and the edge detecting means provides a delay circuit which makes the phase of the inputted serial random data lag, and an exclusive-or (EX-OR) circuit to which the inputted serial random data and pulses that the inputted serial random data are made to lag at the delay circuit are inputted. And the clock recovery circuit further provides a first AND circuit which applies AND to the edge pulses, a fifth clock pulse lagged by xcfx80/8 phase for a fifth reference clock signal lagged by xcfx80 phase for a first reference clock signal, and an eighth clock pulse lagged by xcfx80/8 phase for an eighth reference clock signal lagged by 7xcfx80/4 phase for the first reference clock signal, a second AND circuit which applies AND to the edge pulses, a first clock pulse lagged by xcfx80/8 phase for the first reference clock signal, and a sixth clock pulse lagged by xcfx80/8 phase for a sixth reference clock signal lagged by 5xcfx80/4 phase for the first reference clock signal, a third AND circuit which applies AND to the edge pulses, a second clock pulse lagged by xcfx80/8 phase for a second reference clock signal lagged by xcfx80/4 phase for the first reference clock signal, and a seventh clock pulse lagged by xcfx80/8 phase for a seventh reference clock signal lagged by 3xcfx80/2 phase for the first reference clock signal, a fourth AND circuit which applies AND to the edge pulses, a third clock pulse lagged by xcfx80/8 phase for a third reference clock signal lagged by xcfx80/2 phase for the first reference clock signal, and the eighth clock pulse lagged by xcfx80/8 phase for the eighth reference clock signal lagged by 7xcfx80/4 phase for the first reference clock signal, a fifth AND circuit which applies AND to the edge pulses, a fourth clock pulse lagged by xcfx80/8 phase for a fourth reference clock signal lagged by 3xcfx80/4 phase for the first reference clock signal, and the first clock pulse lagged by xcfx80/8 phase for the first reference clock signal, a sixth AND circuit which applies AND to the edge pulses, the fifth clock pulse lagged by xcfx80/8 phase for the fifth reference clock signal lagged by xcfx80 phase for the first reference clock signal, and the second clock pulse lagged by xcfx80/8 phase for the second reference clock signal lagged by xcfx80/4 phase for the first reference clock signal, a seventh AND circuit which applies AND to the edge pulses, the sixth clock pulse lagged by xcfx80/8 phase for the sixth reference clock signal lagged by 5xcfx80/4 phase for the first reference clock signal, and the third clock pulse lagged by xcfx80/8 phase for the third reference clock signal lagged by xcfx80/2 phase for the first reference clock signal, an eighth AND circuit which applies AND to the edge pulses, the seventh clock pulse lagged by xcfx80/8 phase for the seventh reference clock signal lagged by 3xcfx80/2 phase for the first reference clock signal, and the fourth clock pulse lagged by xcfx80/8 phase for the fourth reference clock signal lagged by 3xcfx80/4 phase for the first reference clock signal, a first set-reset flip flop (SR-F/F) whose set terminal outputs from the first AND circuit are inputted to and whose reset terminal the first clock pulse is inputted to, a second SR-F/F whose set terminal outputs from the second AND circuit are inputted to and whose reset terminal the second clock pulse is inputted to, a third SR-F/F whose set terminal outputs from the third AND circuit are inputted to and whose reset terminal the third clock pulse is inputted to, a fourth SR-F/F whose set terminal outputs from the fourth AND circuit are inputted to and whose reset terminal the fourth clock pulse is inputted to, a fifth SR-F/F whose set terminal outputs from the fifth AND circuit are inputted to and whose reset terminal the fifth clock pulse is inputted to, a sixth SR-F/F whose set terminal outputs from the sixth AND circuit are inputted to and whose reset terminal the sixth clock pulse is inputted to, a seventh SR-F/F whose set terminal outputs from the seventh AND circuit are inputted to and whose reset terminal the seventh clock pulse is inputted to, an eighth SR-F/F whose set terminal outputs from the eighth AND circuit are inputted to and whose reset terminal the eighth clock pulse is inputted to, a first delay circuit which makes outputs from the first SR-F/F lag by xcfx80/8 phase, a second delay circuit which makes outputs from the second SR-F/F lag by xcfx80/8 phase, a third delay circuit which makes outputs from the third SR-F/F lag by xcfx80/8 phase, a fourth delay circuit which makes outputs from the fourth SR-F/F lag by xcfx80/8 phase, a fifth delay circuit which makes outputs from the fifth SR-F/F lag by xcfx80/8 phase, a sixth delay circuit which makes outputs from the sixth SR-F/F lag by xcfx80/8 phase, a seventh delay circuit which makes outputs from the seventh SR-F/F lag by xcfx80/8 phase, an eighth delay circuit which makes outputs from the eighth SR-F/F lag by xcfx80/8 phase, a first phase frequency detector (PFD) which compares the phases of pulses outputted from the first delay circuit with the phase of the inverted output pulse from the first SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a second PFD which compares the phases of pulses outputted from the second delay circuit with the phase of the inverted output pulse from the second SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a third PFD which compares the phases of pulses outputted from the third delay circuit with the phase of the inverted output pulse from the third SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a fourth PFD which compares the phases of pulses outputted from the fourth delay circuit with the phase of the inverted output pulse from the fourth SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a fifth PFD which compares the phases of pulses outputted from the fifth delay circuit with the phase of the inverted output pulse from the fifth SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a sixth PFD which compares the phases of pulses outputted from the sixth delay circuit with the phase of the inverted output pulse from the sixth SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, a seventh PFD which compares the phases of pulses outputted from the seventh delay circuit with the phase of the inverted output pulse from the seventh SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses, and an eighth PFD which compares the phases of pulses outputted from the eighth delay circuit with the phase of the inverted output pulse from the eighth SR-F/F and outputs pulses of the pulse widths in proportion to the phase difference between the compared pulses.
According to a sixth aspect of the present invention, there is provided a phase detecting method, which is performed by phase frequency detectors that compare a phase of a reference clock signal whose frequency is controlled to be about f/2 Hz for inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bit per second (bps) with phases of the inputted serial random data and output pulses of the pulse widths in proportion to the phase difference between the compared result pulses of the reference clock signal and the inputted serial random data. The phase detecting method provides the steps of: generating multi clock signals being the reference clock signal whose frequency is controlled to be about f/2 Hz for the inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bps, and a plurality of clock pulses whose phases are different from the reference clock signal, detecting edges of rising edges and falling edges of the inputted serial random data, selecting whether the detected edges of the inputted serial random data are compared their phases with rising edges or falling edges of the reference clock signal, and outputting first edge pulses synchronized with edges which are judged to be compared their phases with the rising edges of the reference clock signal and second edge pulses synchronized with edges which are judged to be compared their phases with the falling edges of the reference clock signal, edge position correcting so that the frequency of a first clock pulse becomes equal to the frequency of the first edge pulses by selecting only edges of the first clock pulses which perform phase comparison with the first edge pulses in the edges of the first clock pulses which are used at the phase comparison with the rising edges of the reference clock signals, and making edges of the first edge pulses lag by phase difference between the reference clock signal and the first clock pulse, edge position correcting so that the frequency of a second clock pulses becomes equal to the frequency of the second edge pulses by selecting only edges of the second clock pulses which perform phase comparison with the second edge pulses in the edges of the second clock pulses which are used at the phase comparison with the falling edges of the reference clock signal, and making edges of the second edge pulses lag by phase difference between the reference clock signal and the second clock pulse, detecting phase frequency for comparing phases between the first clock pulses whose frequency is equal to the frequency of the first edge pulses, outputted at the edge position correcting, and the first edge pulses whose phases are made to lag by the phase difference, and outputting pulses of the pulse widths in proportion to the phase difference between the both pulses, and detecting phase frequency for comparing phases between the second clock pulses whose frequency is equal to the frequency of the second edge pulses, outputted at the edge position correcting, and the second edge pulses whose phases are made to lag by the phase difference, and outputting pulses of the pulse widths in proportion to the phase difference between the both pulses.
According to a seventh aspect of the present invention, there is provided a phase detecting method, which is performed by phase frequency detectors that compare phases of reference clock signals whose frequency is controlled to be about f/n (n is an integer) Hz for inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bit per second (bps) with phases of the inputted serial random data and output pulses of the pulse widths in proportion to the phase difference between the compared result pulses of the reference clock signals and the inputted serial random data. The phase detecting method provides the steps of: generating multi phase clock signals being a plurality of reference clock signals whose phases are serially different respectively and whose frequency is controlled to be about f/n Hz for inputted serial random data whose data rate is xe2x80x9cfxe2x80x9d bit per second (bps), and a plurality of clock pulses whose phases are different from the plurality of reference clock signals by a designated value, detecting edges of rising edges and falling edges of the inputted serial random data and generating edge pulses synchronized with the rising and falling edges, selecting detected edges of the inputted serial random data at the detecting edges are compared their phases with any of the reference clock signals generated at the multi phase clock generating, and outputting edge pulses synchronized with selected edges of the inputted serial random data in each reference clock signal, edge position correcting so that the frequency of the clock pulses becomes equal to the frequency of edge pulses by selecting only edges using for phase comparison with the edge pulses in the edges of the clock pulses set each of the reference clock signals which are used at the phase comparison with edge pulses generated each of the reference clock signals, and making edges of the edge pulses lag by phase difference between the reference clock signals and the clock pulses set each of the reference clock signals, and detecting phase frequency for comparing phases between the clock pulses whose frequency is equal to the frequency of the edge pulses, outputted at the edge position correcting, and the edge pulses whose phases are made to lag by the phase difference, and outputting pulses of the pulse widths in proportion to the phase difference between the both pulses.